Design of a Power-Efficient 18-Transistor Flip-Flop Architecture for High-Performance Low-Power VLSI Applications
P. Bhagyalakshmi; R. Shirisha; K. Sudheer; N. Karthik Kumar
- Published
- Publisher
- IEEE
- Journal / collection
- 2026 International Conference on Computer Networks and Inventive Communication Technologies (ICCNCT)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/iccnct68477.2026.11589993
The original publisher provides the full text and its access options.
Cite this source
P. Bhagyalakshmi; R. Shirisha; K. Sudheer; N. Karthik Kumar. Design of a Power-Efficient 18-Transistor Flip-Flop Architecture for High-Performance Low-Power VLSI Applications. 2026 International Conference on Computer Networks and Inventive Communication Technologies (ICCNCT). 2026-05-11. https://doi.org/10.1109/iccnct68477.2026.11589993