Design and Integration of High-Efficiency Full Adder Design Using Pass Transistor Logic
Nikhel Mehra; Gaurav Hepat; Preeti Sharma; Menka Yadav
- Published
- Publisher
- IEEE
- Journal / collection
- 2025 IEEE International Symposium on Smart Electronic Systems (iSES)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/ises67504.2025.00047
The original publisher provides the full text and its access options.
Cite this source
Nikhel Mehra; Gaurav Hepat; Preeti Sharma; Menka Yadav. Design and Integration of High-Efficiency Full Adder Design Using Pass Transistor Logic. 2025 IEEE International Symposium on Smart Electronic Systems (iSES). 2025-12-13. https://doi.org/10.1109/ises67504.2025.00047