4F 2 DRAM Integration with Vertical Gate (VG) Cell Transistor and Peri-Under-Cell (PUC) Architecture
Joodong Park; Junhwe Cha; Jin Sun Cho; Seung Wan Chu; Chansun Hyun; Daeik Kim; Ildo Kim; Jiwoo Kim; Sein Kwon; Junghak Lee; Seung Cheol Lee; Ju Hyun Myung; Jino Song; Minchul Sung; Jiho Kang; Suock Chung; Kyunghoon Kim; Seungbum Kim; Seon Soon Kim; Seiyon Kim
- Published
- Publisher
- IEEE
- Journal / collection
- 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.23919/vlsitechnologyandcir65189.2025.11075066
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Cite this source
Joodong Park; Junhwe Cha; Jin Sun Cho; Seung Wan Chu; Chansun Hyun; Daeik Kim; Ildo Kim; Jiwoo Kim; Sein Kwon; Junghak Lee; Seung Cheol Lee; Ju Hyun Myung; Jino Song; Minchul Sung; Jiho Kang; Suock Chung; Kyunghoon Kim; Seungbum Kim; Seon Soon Kim; Seiyon Kim. 4F 2 DRAM Integration with Vertical Gate (VG) Cell Transistor and Peri-Under-Cell (PUC) Architecture. 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). 2025-06-08. https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075066