Topology-Aware Layout Design for Area-Decoupled Transistor Sizing in Multitier CFET SRAM
Yutian Zhang; Jiaquan Fang; Khawar Sarfraz; Mansun Chan
- Published
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Journal / collection
- IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.1109/jxcdc.2026.3709007
The original publisher provides the full text and its access options.
Cite this source
Yutian Zhang; Jiaquan Fang; Khawar Sarfraz; Mansun Chan. Topology-Aware Layout Design for Area-Decoupled Transistor Sizing in Multitier CFET SRAM. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits. 2026. https://doi.org/10.1109/jxcdc.2026.3709007