Energy-efficient redundant transition-free TSPC dual-edge flip-flop design with single-transistor clocked buffer
Tagore Rishil Charugundla; G. Chaitanya Reddy
- Published
- Publisher
- AIP Publishing
- Journal / collection
- AIP Conference Proceedings
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1063/5.0343983
The original publisher provides the full text and its access options.
Cite this source
Tagore Rishil Charugundla; G. Chaitanya Reddy. Energy-efficient redundant transition-free TSPC dual-edge flip-flop design with single-transistor clocked buffer. AIP Conference Proceedings. 2026. https://doi.org/10.1063/5.0343983