Silicon-on-Insulator Pixel FinFET Technology for a High Conversion Gain and Low Dark Noise 2-Layer Transistor Pixel Stacked CIS
R. Takayanagi; T. Kamo; R. Yamachi; M. Sakurai; H. Oishi; T. Iriguchi; H. Takahashi; T. Enomoto; Y. Kageyama; Y. Tanaka; Y. Kikuchi; J. Yamamoto; H. Kumano; S. Yoshida; T. Yamamoto; S. Kawamoto; Y. Murakawa; H. Mizuno; T. Nagaki; H. Tomita
- Published
- Publisher
- IEEE
- Journal / collection
- 2025 IEEE International Electron Devices Meeting (IEDM)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/iedm50572.2025.11353596
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Cite this source
R. Takayanagi; T. Kamo; R. Yamachi; M. Sakurai; H. Oishi; T. Iriguchi; H. Takahashi; T. Enomoto; Y. Kageyama; Y. Tanaka; Y. Kikuchi; J. Yamamoto; H. Kumano; S. Yoshida; T. Yamamoto; S. Kawamoto; Y. Murakawa; H. Mizuno; T. Nagaki; H. Tomita. Silicon-on-Insulator Pixel FinFET Technology for a High Conversion Gain and Low Dark Noise 2-Layer Transistor Pixel Stacked CIS. 2025 IEEE International Electron Devices Meeting (IEDM). 2025-12-06. https://doi.org/10.1109/iedm50572.2025.11353596