Design and Validation of Low Power and Area Efficient 9 Transistor SRAM Using 45nm Technology
Garaga Sowjanya; M. Suneetha
- Published
- Publisher
- IEEE
- Journal / collection
- 2025 6th International Conference on Data Intelligence and Cognitive Informatics (ICDICI)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/icdici66477.2025.11135348
The original publisher provides the full text and its access options.
Cite this source
Garaga Sowjanya; M. Suneetha. Design and Validation of Low Power and Area Efficient 9 Transistor SRAM Using 45nm Technology. 2025 6th International Conference on Data Intelligence and Cognitive Informatics (ICDICI). 2025-07-09. https://doi.org/10.1109/icdici66477.2025.11135348