Four-Level Stacked Si 0.7 Ge 0.3 Channel Gate-All-Around Transistor Using Novel Channel Release and Passivation Technology
Xiaofeng Jia; Fei Zhao; Kaimin Feng; Shuai Yang; Jiahan Yu; Yihong Lu; Haoyan Liu; Yongliang Li
- Published
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Journal / collection
- IEEE Transactions on Electron Devices
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.1109/ted.2026.3658418
The original publisher provides the full text and its access options.
Cite this source
Xiaofeng Jia; Fei Zhao; Kaimin Feng; Shuai Yang; Jiahan Yu; Yihong Lu; Haoyan Liu; Yongliang Li. Four-Level Stacked Si 0.7 Ge 0.3 Channel Gate-All-Around Transistor Using Novel Channel Release and Passivation Technology. IEEE Transactions on Electron Devices. 2026-03. https://doi.org/10.1109/ted.2026.3658418