Low Power High Speed Finfet Dram Cell and 4x4 Array Design Using the Sleep Transistor Technique
N. Praveena; N. Shylashree
- Published
- Publisher
- Engineering, Technology & Applied Science Research
- Journal / collection
- Engineering, Technology & Applied Science Research
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.48084/etasr.15183
The original publisher provides the full text and its access options.
Cite this source
N. Praveena; N. Shylashree. Low Power High Speed Finfet Dram Cell and 4x4 Array Design Using the Sleep Transistor Technique. Engineering, Technology & Applied Science Research. 2026-04-04. https://doi.org/10.48084/etasr.15183