First Demonstration of Monolithic 3-Tier Nanosheet Transistor Stacking with Split Gate Featuring Tri-State Inverter/Half Sram Functionalities
Bo-Wei Huang; Ying-Qi Liu; Ching-Wang Yao; Wei-Jen Chen; Min-Kuan Lin; Xin-Yuan Lin; Chun-Yi Cheng; Yi Huang; Ding-Wei Lin; Chih-Hsuan Lu; Tsung-Han Tsai; C. W. Liu
- Published
- Publisher
- IEEE
- Journal / collection
- 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.23919/vlsitechnologyandcir65189.2025.11074914
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Cite this source
Bo-Wei Huang; Ying-Qi Liu; Ching-Wang Yao; Wei-Jen Chen; Min-Kuan Lin; Xin-Yuan Lin; Chun-Yi Cheng; Yi Huang; Ding-Wei Lin; Chih-Hsuan Lu; Tsung-Han Tsai; C. W. Liu. First Demonstration of Monolithic 3-Tier Nanosheet Transistor Stacking with Split Gate Featuring Tri-State Inverter/Half Sram Functionalities. 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). 2025-06-08. https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074914