A transistor-stacking-based SRAM architecture for power reduction with high speed and high reliability
Shuo Cai; Zhu Huang; Maoxuan Wei; Fei Yu
- Published
- Publisher
- Elsevier BV
- Journal / collection
- Microelectronics Reliability
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.1016/j.microrel.2026.116182
The original publisher provides the full text and its access options.
Cite this source
Shuo Cai; Zhu Huang; Maoxuan Wei; Fei Yu. A transistor-stacking-based SRAM architecture for power reduction with high speed and high reliability. Microelectronics Reliability. 2026-07. https://doi.org/10.1016/j.microrel.2026.116182