DESIGN AND DELIBERATION OF A TEN-TRANSISTOR SRAM CELL EMPLOYING HALF-VDD ROW-WISE DYNAMIC PRECHARGE FOR DIMINISHED SWITCHING POWER AND ULTRALOW READ BIT-LINE LEAKAGE
K DEVAKI DEVI; M ANUSHA; S RUCHITHA; K MOUNIKA; G GOWTHAMI
- Published
- Publisher
- MSR Edusoft Private Limited
- Journal / collection
- Journal of Science Engineering Technology and Management Sciences
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.64771/jsetms.2026.v03.i01.pp73-80
The original publisher provides the full text and its access options.
Cite this source
K DEVAKI DEVI; M ANUSHA; S RUCHITHA; K MOUNIKA; G GOWTHAMI. DESIGN AND DELIBERATION OF A TEN-TRANSISTOR SRAM CELL EMPLOYING HALF-VDD ROW-WISE DYNAMIC PRECHARGE FOR DIMINISHED SWITCHING POWER AND ULTRALOW READ BIT-LINE LEAKAGE. Journal of Science Engineering Technology and Management Sciences. 2026-02. https://doi.org/10.64771/jsetms.2026.v03.i01.pp73-80