A Comprehensive Study of the Current Paths of HV IO Transistor During the Latch-Up Test
Jian-Hsing Lee; Chien-Wei Wang; Hsien-Feng Liao; Chih-Hsuan Lin; Karuna Nidhi; Yeh-Jen Huang; Yeh-Ning Jou; Chih-Cherng Liao; Ke-Horng Chen
- Published
- Publisher
- IEEE
- Journal / collection
- 2025 IEEE 32nd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/ipfa65338.2025.11256740
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Cite this source
Jian-Hsing Lee; Chien-Wei Wang; Hsien-Feng Liao; Chih-Hsuan Lin; Karuna Nidhi; Yeh-Jen Huang; Yeh-Ning Jou; Chih-Cherng Liao; Ke-Horng Chen. A Comprehensive Study of the Current Paths of HV IO Transistor During the Latch-Up Test. 2025 IEEE 32nd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA). 2025-08-05. https://doi.org/10.1109/ipfa65338.2025.11256740