Process Insights into 3D-DRAM with Vertical Bit Line and Scalable GAA Transistor
N. Rassoul; L. A. Labbate; G. Eneman; A. Fantini; R. Ritzenthaler; J. Loyo Prado; R. Loo; W. Devulder; E. Dupuy; T. Peissker; A. Pacco; H. K. Raut; P. Eyben; E. Canga; E. Rosseel; A. Sharma; H. Oh; Y. Rawal; M. Beggiato; J. Kim
- Published
- Publisher
- IEEE
- Journal / collection
- 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.23919/vlsitechnologyandcir65189.2025.11075009
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Cite this source
N. Rassoul; L. A. Labbate; G. Eneman; A. Fantini; R. Ritzenthaler; J. Loyo Prado; R. Loo; W. Devulder; E. Dupuy; T. Peissker; A. Pacco; H. K. Raut; P. Eyben; E. Canga; E. Rosseel; A. Sharma; H. Oh; Y. Rawal; M. Beggiato; J. Kim. Process Insights into 3D-DRAM with Vertical Bit Line and Scalable GAA Transistor. 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). 2025-06-08. https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075009