A 16nm pFET Floating Gate Transistor Enabling Programmable Analog Design in a FinFET Logic CMOS Process
Praveen Raj Ayyappan; Afolabi Ige; Pranav O. Mathews; Linhao Yang; Jennifer O. Hasler
- Published
- Publisher
- IEEE
- Journal / collection
- 2025 IEEE European Solid-State Electronics Research Conference (ESSERC)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/esserc66193.2025.11214091
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Cite this source
Praveen Raj Ayyappan; Afolabi Ige; Pranav O. Mathews; Linhao Yang; Jennifer O. Hasler. A 16nm pFET Floating Gate Transistor Enabling Programmable Analog Design in a FinFET Logic CMOS Process. 2025 IEEE European Solid-State Electronics Research Conference (ESSERC). 2025-09-08. https://doi.org/10.1109/esserc66193.2025.11214091