Design of Efficient Multiplier with Low Power and High-Speed Using PTL (Pass Transistor Logic)
D. Satyanarayana
- Published
- Publisher
- Science Research Society
- Journal / collection
- Communications on Applied Nonlinear Analysis
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.52783/cana.v32.5231
The original publisher provides the full text and its access options.
Cite this source
D. Satyanarayana. Design of Efficient Multiplier with Low Power and High-Speed Using PTL (Pass Transistor Logic). Communications on Applied Nonlinear Analysis. 2025-04-28. https://doi.org/10.52783/cana.v32.5231