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Performance Assessment of CMOS and Pass-Transistor Logic based Full Adder Architectures for Low-Power Digital Systems

K.Lokesh Krishna; M.Anjaneya Naik

Published
Publisher
IEEE
Journal / collection
2026 8th International Conference on Inventive Material Science and Applications (ICIMA)
Research area
Semiconductors
Source type
Conference paper
DOI
10.1109/icima68728.2026.11564705

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K.Lokesh Krishna; M.Anjaneya Naik. Performance Assessment of CMOS and Pass-Transistor Logic based Full Adder Architectures for Low-Power Digital Systems. 2026 8th International Conference on Inventive Material Science and Applications (ICIMA). 2026-05-13. https://doi.org/10.1109/icima68728.2026.11564705

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