Design Considerations for High Performance Vertical Channel DRAM Cell Array Transistor
Moonyoung Jeong; Kilho Yu; Yootak Jun; Jae-Hyun Choi; Seungwoo Park; Junsoo Kim; Jeonghoon Oh; Segeun Park; Jaihyuk Song
- Published
- Publisher
- IEEE
- Journal / collection
- 2026 IEEE International Memory Workshop (IMW)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/imw68301.2026.11532790
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Cite this source
Moonyoung Jeong; Kilho Yu; Yootak Jun; Jae-Hyun Choi; Seungwoo Park; Junsoo Kim; Jeonghoon Oh; Segeun Park; Jaihyuk Song. Design Considerations for High Performance Vertical Channel DRAM Cell Array Transistor. 2026 IEEE International Memory Workshop (IMW). 2026-05-10. https://doi.org/10.1109/imw68301.2026.11532790