Low-Power Digital Circuit Design: Evaluating Pass - Transistor Logic and CMOS for Power-Delay Optimization
Jerim Justin; Vijayasri P
- Published
- Publisher
- IEEE
- Journal / collection
- 2025 8th International Conference on Circuit, Power & Computing Technologies (ICCPCT)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/iccpct65132.2025.11176668
The original publisher provides the full text and its access options.
Cite this source
Jerim Justin; Vijayasri P. Low-Power Digital Circuit Design: Evaluating Pass - Transistor Logic and CMOS for Power-Delay Optimization. 2025 8th International Conference on Circuit, Power & Computing Technologies (ICCPCT). 2025-08-07. https://doi.org/10.1109/iccpct65132.2025.11176668