Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis
Anup Kumar Biswas; Dimitri Kagaris
- Published
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Journal / collection
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.1109/tcad.2025.3538492
The original publisher provides the full text and its access options.
Cite this source
Anup Kumar Biswas; Dimitri Kagaris. Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2025-08. https://doi.org/10.1109/tcad.2025.3538492