Power–Delay Optimized Full Adder Architecture based on Pass Transistor Logic
D. Srilatha; K. Lokesh Krishna; I. Kundana Sindu; K. Sai Mahesh; B.Sree Harsha; K. Haritha Reddy
- Published
- Publisher
- IEEE
- Journal / collection
- 2026 International Conference on Smart Electronic Devices and Intelligent Systems (ICSEDIS)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/icsedis68157.2026.11518313
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Cite this source
D. Srilatha; K. Lokesh Krishna; I. Kundana Sindu; K. Sai Mahesh; B.Sree Harsha; K. Haritha Reddy. Power–Delay Optimized Full Adder Architecture based on Pass Transistor Logic. 2026 International Conference on Smart Electronic Devices and Intelligent Systems (ICSEDIS). 2026-04-13. https://doi.org/10.1109/icsedis68157.2026.11518313