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Speed and Power Optimized Pass Transistor Logic Multiplier Using Cascaded Compressor

Kakarla Deepti; S.Aruna Deepthi; B.Srinivasa Rao; Vibha.D. Kulkarni; M. Chandrika; Meharunnisa

Published
Publisher
IEEE
Journal / collection
2025 5th IEEE International Conference on Applied Electromagnetics, Signal Processing, & Communication (AESPC)
Research area
Semiconductors
Source type
Conference paper
DOI
10.1109/aespc67542.2025.11326720

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Kakarla Deepti; S.Aruna Deepthi; B.Srinivasa Rao; Vibha.D. Kulkarni; M. Chandrika; Meharunnisa. Speed and Power Optimized Pass Transistor Logic Multiplier Using Cascaded Compressor. 2025 5th IEEE International Conference on Applied Electromagnetics, Signal Processing, & Communication (AESPC). 2025-12-05. https://doi.org/10.1109/aespc67542.2025.11326720

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