Design and Analysis of a GHz PLL Using GDI and Pass Transistor Based PFD with a Lock Time of 520 ns
Dheeraj Singh Rajput; Bharat Choudhary; Archana Singhal; D. Boolchandani
- Published
- Publisher
- IEEE
- Journal / collection
- 2025 IEEE International Symposium on Smart Electronic Systems (iSES)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/ises67504.2025.00053
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Cite this source
Dheeraj Singh Rajput; Bharat Choudhary; Archana Singhal; D. Boolchandani. Design and Analysis of a GHz PLL Using GDI and Pass Transistor Based PFD with a Lock Time of 520 ns. 2025 IEEE International Symposium on Smart Electronic Systems (iSES). 2025-12-13. https://doi.org/10.1109/ises67504.2025.00053