Block-Level Design Optimization for Sub-100-nm Cell Height Libraries with Stacked Transistor
N. Lanzillo; J. Mazza; S. Khan; H. Shin; J. Lim; Y.G. Park; U. Bajpai; J. Wilson; H. Trombley; J. Stuffle; N. Perez; S. Fan; J. Zhang; T. Yamashita; G. Shahidi; D. Guo; K. Seo; D. Dechene; K. Rim; H. Bu
- Published
- Publisher
- IEEE
- Journal / collection
- 2025 IEEE International Electron Devices Meeting (IEDM)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/iedm50572.2025.11353683
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Cite this source
N. Lanzillo; J. Mazza; S. Khan; H. Shin; J. Lim; Y.G. Park; U. Bajpai; J. Wilson; H. Trombley; J. Stuffle; N. Perez; S. Fan; J. Zhang; T. Yamashita; G. Shahidi; D. Guo; K. Seo; D. Dechene; K. Rim; H. Bu. Block-Level Design Optimization for Sub-100-nm Cell Height Libraries with Stacked Transistor. 2025 IEEE International Electron Devices Meeting (IEDM). 2025-12-06. https://doi.org/10.1109/iedm50572.2025.11353683