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Research literature / Conference paper

Design and System Level Validation of a Truth Table Synthesized 18 Transistor Full Adder for Binary Accumulation Application

Yatham Srinivas; Orus Lalitha; Avireni Srinivasulu; Bhargav Appasani; Cristian Ravariu

Published
Publisher
IEEE
Journal / collection
2026 18th International Conference on Electronics, Computers and Artificial Intelligence (ECAI)
Research area
Semiconductors
Source type
Conference paper
DOI
10.1109/ecai69016.2026.11613780

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Yatham Srinivas; Orus Lalitha; Avireni Srinivasulu; Bhargav Appasani; Cristian Ravariu. Design and System Level Validation of a Truth Table Synthesized 18 Transistor Full Adder for Binary Accumulation Application. 2026 18th International Conference on Electronics, Computers and Artificial Intelligence (ECAI). 2026-07. https://doi.org/10.1109/ecai69016.2026.11613780

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