A Novel 3D AND-Type 1T1C DRAM Architecture with Local Bitline Transistor (BLT) to Reduce the Bitline Capacitance (C BL ) for Enhanced Sensing Window in High-Layer Stacked 3D DRAM
Hang-Ting Lue; Teng-Hao Yeh; Wei-Chen Chen; Keh-Chung Wang; Chih-Yuan Lu
- Published
- Publisher
- IEEE
- Journal / collection
- 2026 IEEE International Memory Workshop (IMW)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/imw68301.2026.11532892
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Cite this source
Hang-Ting Lue; Teng-Hao Yeh; Wei-Chen Chen; Keh-Chung Wang; Chih-Yuan Lu. A Novel 3D AND-Type 1T1C DRAM Architecture with Local Bitline Transistor (BLT) to Reduce the Bitline Capacitance (C BL ) for Enhanced Sensing Window in High-Layer Stacked 3D DRAM. 2026 IEEE International Memory Workshop (IMW). 2026-05-10. https://doi.org/10.1109/imw68301.2026.11532892