Study of 3-D Line Edge Roughness (LER) in Vertical Channel Array Transistor for DRAM
Jaehyuk Lim; Seokchan Yoon; Juho Sung; Sanghyun Kang; Gwon Kim; Hyoung Won Baac; Changhwan Shin
- Published
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Journal / collection
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.1109/tcad.2025.3546195
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Cite this source
Jaehyuk Lim; Seokchan Yoon; Juho Sung; Sanghyun Kang; Gwon Kim; Hyoung Won Baac; Changhwan Shin. Study of 3-D Line Edge Roughness (LER) in Vertical Channel Array Transistor for DRAM. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2025-09. https://doi.org/10.1109/tcad.2025.3546195