Gate-All-Around Vertically Stacked Polycrystalline Silicon Nanosheet Channels Transistor Fabricated Using Low-Pressure and Low-Thermal-Budget Solid-Phase Crystallization Without Channel Trimming Processes
Po-Yi Kuo; Chou-Wei Wang
- Published
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Journal / collection
- IEEE Journal of the Electron Devices Society
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.1109/jeds.2026.3736437
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Cite this source
Po-Yi Kuo; Chou-Wei Wang. Gate-All-Around Vertically Stacked Polycrystalline Silicon Nanosheet Channels Transistor Fabricated Using Low-Pressure and Low-Thermal-Budget Solid-Phase Crystallization Without Channel Trimming Processes. IEEE Journal of the Electron Devices Society. 2026. https://doi.org/10.1109/jeds.2026.3736437