Novel Ultra-Thin Transistor Layer Transfer (TLT) Technology for Demonstrating Wafer-Level nm-Scale 3-Layer Stacking to Enable Multi-Tier Transistors and Backside PDN of a 3D Vertical FET Architecture
C.-L. Lu; Hankel C.-H. Chang; Y.-C. Lin; P.-R. Ni; C.-H. Chuang; H. Henck; C.-Y. Chuang; S.-C. Lin; H.-S. Huang; L.-H. Chiu; Y.-C. Sun; K.-Y. Shih; I. Radu; Bich-Yen Nguyen; S.-Z. Chang
- Published
- Publisher
- IEEE
- Journal / collection
- 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.23919/vlsitechnologyandcir65189.2025.11074821
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Cite this source
C.-L. Lu; Hankel C.-H. Chang; Y.-C. Lin; P.-R. Ni; C.-H. Chuang; H. Henck; C.-Y. Chuang; S.-C. Lin; H.-S. Huang; L.-H. Chiu; Y.-C. Sun; K.-Y. Shih; I. Radu; Bich-Yen Nguyen; S.-Z. Chang. Novel Ultra-Thin Transistor Layer Transfer (TLT) Technology for Demonstrating Wafer-Level nm-Scale 3-Layer Stacking to Enable Multi-Tier Transistors and Backside PDN of a 3D Vertical FET Architecture. 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). 2025-06-08. https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074821