Analyzing Noise Margin Degradation in Subthreshold Nanosheet Transistor Logic Gates: An Interface Quasi-Fermi Potential Model for Interface-trapped Charge Effects
Juin J. Liou; Yimu Yang; Te-Kuang Chiang
- Published
- Publisher
- MYU K.K.
- Journal / collection
- Sensors and Materials
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.18494/sam5534
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Cite this source
Juin J. Liou; Yimu Yang; Te-Kuang Chiang. Analyzing Noise Margin Degradation in Subthreshold Nanosheet Transistor Logic Gates: An Interface Quasi-Fermi Potential Model for Interface-trapped Charge Effects. Sensors and Materials. 2025-07-04. https://doi.org/10.18494/sam5534