A Compact 4T+2T SRAM-Based Digital Compute-in-Memory Bitcell with Reduced Transistor Count for Energy-Efficient Bitwise MAC Operations in 45 nm CMOS
Shamanth Hariprasad; Srinivas Balasubramanian; Adnan A. Patel; Kyuwon Ken Choi
- Published
- Publisher
- MDPI AG
- Journal / collection
- Electronics
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.3390/electronics15122630
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Cite this source
Shamanth Hariprasad; Srinivas Balasubramanian; Adnan A. Patel; Kyuwon Ken Choi. A Compact 4T+2T SRAM-Based Digital Compute-in-Memory Bitcell with Reduced Transistor Count for Energy-Efficient Bitwise MAC Operations in 45 nm CMOS. Electronics. 2026-06-14. https://doi.org/10.3390/electronics15122630