Constrained Bayesian optimization using a Lagrange multiplier applied to power transistor design
Ping-Ju Chuang; Ali Saadat; Sara Ghazvini; Hal Edwards; William G. Vandenberghe
- Published
- Publisher
- Springer Science and Business Media LLC
- Journal / collection
- Journal of Computational Electronics
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.1007/s10825-025-02356-9
The original publisher provides the full text and its access options.
Cite this source
Ping-Ju Chuang; Ali Saadat; Sara Ghazvini; Hal Edwards; William G. Vandenberghe. Constrained Bayesian optimization using a Lagrange multiplier applied to power transistor design. Journal of Computational Electronics. 2025-07-21. https://doi.org/10.1007/s10825-025-02356-9