Electrical Characteristics of the 4F 2 Vertical Gate (VG) DRAM integrated with Bit Line Shielding (BLS) and Back Gate (BG) Transistor
Seung Wan Chu; Junho Cheon; Jinsun Cho; Eunhyup Doh; Jungmin Han; Seung Bum Hong; Choong-ki Kim; Daeik Kim; Jin Ar Kim; Sunghyun Kim; Yongtaik Kim; Kyongsoo Kum; Sein Kwon; DongJae Lee; Dong Ryeol Lee; Junghak Lee; Eunshil Park; Jongbum Park; Dong Hee Shin; Eunji Shin
- Published
- Publisher
- IEEE
- Journal / collection
- 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/vlsitechnologyandcir65830.2026.11577266
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Seung Wan Chu; Junho Cheon; Jinsun Cho; Eunhyup Doh; Jungmin Han; Seung Bum Hong; Choong-ki Kim; Daeik Kim; Jin Ar Kim; Sunghyun Kim; Yongtaik Kim; Kyongsoo Kum; Sein Kwon; DongJae Lee; Dong Ryeol Lee; Junghak Lee; Eunshil Park; Jongbum Park; Dong Hee Shin; Eunji Shin. Electrical Characteristics of the 4F 2 Vertical Gate (VG) DRAM integrated with Bit Line Shielding (BLS) and Back Gate (BG) Transistor. 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). 2026-06-14. https://doi.org/10.1109/vlsitechnologyandcir65830.2026.11577266