Modeling of Transistor and Interconnect Technologies Targeting Next Generation Logic GAA and CFET Nodes
Ashish Pal; Pratik B. Vyas; Gregory Costrini; El Mehdi Bazizi
- Published
- Publisher
- The Japan Society of Applied Physics
- Journal / collection
- Extended Abstracts of the 2025 International Conference on Solid State Devices and Materials
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.7567/ssdm.2025.a-1-01
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Cite this source
Ashish Pal; Pratik B. Vyas; Gregory Costrini; El Mehdi Bazizi. Modeling of Transistor and Interconnect Technologies Targeting Next Generation Logic GAA and CFET Nodes. Extended Abstracts of the 2025 International Conference on Solid State Devices and Materials. 2025-09-16. https://doi.org/10.7567/ssdm.2025.a-1-01