Modeling Techniques for the Formal Verification of Integrated Circuits at Transistor-Level: Performance Versus Precision Tradeoffs
Oussama Oulkaid; Bruno Ferres; Matthieu Moy; Pascal Raymond; Mehdi Khosravian Ghadikolaei
- Published
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Journal / collection
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.1109/tcad.2025.3608647
The original publisher provides the full text and its access options.
Cite this source
Oussama Oulkaid; Bruno Ferres; Matthieu Moy; Pascal Raymond; Mehdi Khosravian Ghadikolaei. Modeling Techniques for the Formal Verification of Integrated Circuits at Transistor-Level: Performance Versus Precision Tradeoffs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2026-04. https://doi.org/10.1109/tcad.2025.3608647