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Research literature / Conference paper

Fault Simulation Algorithm for Transistor Stuck Fault in VLSI Testing

Madhu Naik Nenavath; Sobhit Saxena; Suman Lata Tripathi

Published
Publisher
IEEE
Journal / collection
2025 Devices for Integrated Circuit (DevIC)
Research area
Semiconductors
Source type
Conference paper
DOI
10.1109/devic63749.2025.11012179

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Madhu Naik Nenavath; Sobhit Saxena; Suman Lata Tripathi. Fault Simulation Algorithm for Transistor Stuck Fault in VLSI Testing. 2025 Devices for Integrated Circuit (DevIC). 2025-04-05. https://doi.org/10.1109/devic63749.2025.11012179

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