SiGe Channel for Scaled Gate-All-Around Nanosheet pFET Transistor for Advanced Logic Applications
S. Mochizuki; S. Kumar; A. Greene; K. Killic; X. Wang; H. Zhou; A. Bryant; J. Li; J. Demarest; E. Leobandung
- Published
- Publisher
- IEEE
- Journal / collection
- 2025 IEEE International Electron Devices Meeting (IEDM)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/iedm50572.2025.11353609
The original publisher provides the full text and its access options.
Cite this source
S. Mochizuki; S. Kumar; A. Greene; K. Killic; X. Wang; H. Zhou; A. Bryant; J. Li; J. Demarest; E. Leobandung. SiGe Channel for Scaled Gate-All-Around Nanosheet pFET Transistor for Advanced Logic Applications. 2025 IEEE International Electron Devices Meeting (IEDM). 2025-12-06. https://doi.org/10.1109/iedm50572.2025.11353609