7.10 A 200MP ${0. 6 1} {\mu} \mathrm{m}$-Pixel-Pitch CMOS Imager with Sub-1e Readout Noise Using Interlaced-Shared Transistor Architecture and On-Chip Motion Artifact-Free HDR Synthesis for 8K Video Applications
Richard Xu; Guanjing Ren; Yaowu Mo; Dekui Qi; Qian Wang; Shengxin Zhang
- Published
- Publisher
- IEEE
- Journal / collection
- 2026 IEEE International Solid-State Circuits Conference (ISSCC)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/isscc49663.2026.11409135
The original publisher provides the full text and its access options.
Cite this source
Richard Xu; Guanjing Ren; Yaowu Mo; Dekui Qi; Qian Wang; Shengxin Zhang. 7.10 A 200MP ${0. 6 1} {\mu} \mathrm{m}$-Pixel-Pitch CMOS Imager with Sub-1e Readout Noise Using Interlaced-Shared Transistor Architecture and On-Chip Motion Artifact-Free HDR Synthesis for 8K Video Applications. 2026 IEEE International Solid-State Circuits Conference (ISSCC). 2026-02-15. https://doi.org/10.1109/isscc49663.2026.11409135