Design and Analysis of a Low-Power Hybrid 10-Transistor CMOS Full Adder in 180 nm Technology
Soniya Patel, Deepali Sahu, Madhu Vishwakarma
- Published
- Publisher
- Naksh Solutions
- Journal / collection
- International Journal of Advanced Research in Science Communication and Technology
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.48175/ijarsct-38248
The original publisher provides the full text and its access options.
Cite this source
Soniya Patel, Deepali Sahu, Madhu Vishwakarma. Design and Analysis of a Low-Power Hybrid 10-Transistor CMOS Full Adder in 180 nm Technology. International Journal of Advanced Research in Science Communication and Technology. 2026-09-11. https://doi.org/10.48175/ijarsct-38248