A 12nm 4Mb 104.56-to-137.75TFLOPS/W Charge-Trap Transistor-Based Computing-in-Memory Macro Using Analog-Predict-Digital-Compute for AI Edge Devices
Junzhe Shen; Zhidao Zhou; Wenfeng Zha; Zhi Li; Weizeng Li; Bohan Wang; Junyu Zhu; Hanghang Gao; Zhongze Han; Yiman Wang; Linfang Wang; Hongyang Hu; Qing Luo; Chunmeng Dou; Ming Liu
- Published
- Publisher
- IEEE
- Journal / collection
- 2026 IEEE International Solid-State Circuits Conference (ISSCC)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/isscc49663.2026.11409272
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Junzhe Shen; Zhidao Zhou; Wenfeng Zha; Zhi Li; Weizeng Li; Bohan Wang; Junyu Zhu; Hanghang Gao; Zhongze Han; Yiman Wang; Linfang Wang; Hongyang Hu; Qing Luo; Chunmeng Dou; Ming Liu. A 12nm 4Mb 104.56-to-137.75TFLOPS/W Charge-Trap Transistor-Based Computing-in-Memory Macro Using Analog-Predict-Digital-Compute for AI Edge Devices. 2026 IEEE International Solid-State Circuits Conference (ISSCC). 2026-02-15. https://doi.org/10.1109/isscc49663.2026.11409272