Optimized ultra-low power and reduced delay GNR Ternary SRAM using a 7-transistor architecture
Ravikishore Gaddikoppula; Nandhitha Nathakattuvalasu Muthu
- Published
- Publisher
- Institute of Advanced Engineering and Science
- Journal / collection
- International Journal of Informatics and Communication Technology (IJ-ICT)
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.11591/ijict.v14i3.pp1044-1055
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Cite this source
Ravikishore Gaddikoppula; Nandhitha Nathakattuvalasu Muthu. Optimized ultra-low power and reduced delay GNR Ternary SRAM using a 7-transistor architecture. International Journal of Informatics and Communication Technology (IJ-ICT). 2025-12-01. https://doi.org/10.11591/ijict.v14i3.pp1044-1055