NanoStack Transistor Architecture for CMOS 7A Node and Beyond
S. Reboh; C. Zhang; T. Yamashita; W. K. Li; R. Xie; T. Ando; U. Bajpai; J. Mazza; N. Lanzillo; E. Cho; H. Zhou; J. Strane; E. Miller; J. Satterlee; S. Fan; Y. Sulehria; M. Sankarapandian; S. Mochizuki; N. Shanker; R. Johnson
- Published
- Publisher
- IEEE
- Journal / collection
- 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.23919/vlsitechnologyandcir65189.2025.11074866
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Cite this source
S. Reboh; C. Zhang; T. Yamashita; W. K. Li; R. Xie; T. Ando; U. Bajpai; J. Mazza; N. Lanzillo; E. Cho; H. Zhou; J. Strane; E. Miller; J. Satterlee; S. Fan; Y. Sulehria; M. Sankarapandian; S. Mochizuki; N. Shanker; R. Johnson. NanoStack Transistor Architecture for CMOS 7A Node and Beyond. 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). 2025-06-08. https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074866