Design and Analysis of a Compact 3:8 Decoder with Reduced Transistor Count for Low Power VLSI Applications
Thumala Obulesu; Kundan Kumar
- Published
- Publisher
- IEEE
- Journal / collection
- 2026 International Conference on Intelligent Processing, Hardware, Electronics, and Radio Systems (CIPHER)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/cipher70417.2026.11523918
The original publisher provides the full text and its access options.
Cite this source
Thumala Obulesu; Kundan Kumar. Design and Analysis of a Compact 3:8 Decoder with Reduced Transistor Count for Low Power VLSI Applications. 2026 International Conference on Intelligent Processing, Hardware, Electronics, and Radio Systems (CIPHER). 2026-02-13. https://doi.org/10.1109/cipher70417.2026.11523918