Design of low power 9 T SRAM cell with high-performance decoder circuit using pass-transistor logic
Sudheer Kumar Matam; Rajesh Kumar Nema
- Published
- Publisher
- Springer Science and Business Media LLC
- Journal / collection
- Analog Integrated Circuits and Signal Processing
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.1007/s10470-026-02624-z
The original publisher provides the full text and its access options.
Cite this source
Sudheer Kumar Matam; Rajesh Kumar Nema. Design of low power 9 T SRAM cell with high-performance decoder circuit using pass-transistor logic. Analog Integrated Circuits and Signal Processing. 2026-08. https://doi.org/10.1007/s10470-026-02624-z