H- SPICE Simulation of Graphene Nanoribbon Field-Effect Transistor Ternary Logic Gates: A Power-Delay Optimal Implementation of Multiple-Valued Logic Circuits
Jetya Banothu¹; Sangeeta Nakhate²
- Published
- Publisher
- Springer Science and Business Media LLC
- Research area
- Semiconductors
- Source type
- Preprint / posted paper
- DOI
- 10.21203/rs.3.rs-9499643/v1
This is a preprint or other posted paper. Check the original source for its review and publication status.
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Cite this source
Jetya Banothu¹; Sangeeta Nakhate². H- SPICE Simulation of Graphene Nanoribbon Field-Effect Transistor Ternary Logic Gates: A Power-Delay Optimal Implementation of Multiple-Valued Logic Circuits. Springer Science and Business Media LLC. 2026-07-01. https://doi.org/10.21203/rs.3.rs-9499643/v1