Access Transistor Analysis of a Proposed 3.5 F 2 DRAM With a Two-Stack Word Line Architecture for Next-Generation Scaling
Jaesun Baek; Bogeun Jo; Hyeok Je Jeong; Bogyeong Kim; Juhui Kim; Yoonwoo Choi; Kwang Ryeol Kim; Chai Rok Lim; Yong Soo Kim; Dae Young Kim; Gi Yeol Yun; Jaehyun Lee
- Published
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Journal / collection
- IEEE Transactions on Electron Devices
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.1109/ted.2025.3607863
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Cite this source
Jaesun Baek; Bogeun Jo; Hyeok Je Jeong; Bogyeong Kim; Juhui Kim; Yoonwoo Choi; Kwang Ryeol Kim; Chai Rok Lim; Yong Soo Kim; Dae Young Kim; Gi Yeol Yun; Jaehyun Lee. Access Transistor Analysis of a Proposed 3.5 F 2 DRAM With a Two-Stack Word Line Architecture for Next-Generation Scaling. IEEE Transactions on Electron Devices. 2025-11. https://doi.org/10.1109/ted.2025.3607863