Design-Technology Co-Optimization: Analysis of Source/Drain Fence for Performance Improvement and Cell Size Scaling in Gate-All-Around Field Effect Transistor-based Circuits
Jaehyuk Lim; Donghwan Han; Changwoo Han; Jungsu Kim; Subin Lim; Seungjoon Jeong; Juho Sung; Changhwan Shin
- Published
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Journal / collection
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.1109/tcad.2026.3681528
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Cite this source
Jaehyuk Lim; Donghwan Han; Changwoo Han; Jungsu Kim; Subin Lim; Seungjoon Jeong; Juho Sung; Changhwan Shin. Design-Technology Co-Optimization: Analysis of Source/Drain Fence for Performance Improvement and Cell Size Scaling in Gate-All-Around Field Effect Transistor-based Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2026. https://doi.org/10.1109/tcad.2026.3681528