Design of Adders Using Pass Transistor Logic for Wallace Tree Multiplier in 45nm Process
Ullas Upendra Achari; Bhaskar Reddy V; M Rajesh Kiran; Aswini N
- Published
- Publisher
- IEEE
- Journal / collection
- 2025 6th International Conference for Emerging Technology (INCET)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/incet64471.2025.11140259
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Cite this source
Ullas Upendra Achari; Bhaskar Reddy V; M Rajesh Kiran; Aswini N. Design of Adders Using Pass Transistor Logic for Wallace Tree Multiplier in 45nm Process. 2025 6th International Conference for Emerging Technology (INCET). 2025-05-23. https://doi.org/10.1109/incet64471.2025.11140259