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Transistor profiling for quantitative evaluation of variability in transistor characteristics due to layout dependent effects (LDEs)

Chikaaki Kodama; Mikiyasu Yamaji; Hiroshi Kitahara; Akira Hokazono; Shigeki Nojima; Piyush Pathak; Kimiko Ichikawa; Jac P. Condella; Michel L. Cote; Ya-Chieh Lai; Philippe Hurat

Published
Publisher
SPIE
Journal / collection
DTCO and Computational Patterning III
Research area
Semiconductors
Source type
Conference paper
DOI
10.1117/12.3010201

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Chikaaki Kodama; Mikiyasu Yamaji; Hiroshi Kitahara; Akira Hokazono; Shigeki Nojima; Piyush Pathak; Kimiko Ichikawa; Jac P. Condella; Michel L. Cote; Ya-Chieh Lai; Philippe Hurat. Transistor profiling for quantitative evaluation of variability in transistor characteristics due to layout dependent effects (LDEs). DTCO and Computational Patterning III. 2024-04-10. https://doi.org/10.1117/12.3010201

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