Resistance Based Drain Current Model of Surrounded Channel Junction Less Field Effect Transistor
Department of Instrumentation Engineering, Central Institute of Technology, Kokrajhar, 783370 Assam, India; N. Das; K. C. D. Sarma; Department of Instrumentation Engineering, Central Institute of Technology, Kokrajhar, 783370 Assam, India
- Published
- Publisher
- Sumy State University
- Journal / collection
- Journal of Nano- and Electronic Physics
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.21272/jnep.16(4).04002
The original publisher provides the full text and its access options.
Cite this source
Department of Instrumentation Engineering, Central Institute of Technology, Kokrajhar, 783370 Assam, India; N. Das; K. C. D. Sarma; Department of Instrumentation Engineering, Central Institute of Technology, Kokrajhar, 783370 Assam, India. Resistance Based Drain Current Model of Surrounded Channel Junction Less Field Effect Transistor. Journal of Nano- and Electronic Physics. 2024. https://doi.org/10.21272/jnep.16(4).04002